View AD5251BRU1_6933692.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

dual 64 - /256 - position i 2 c nonvolatile memory digital potentiometers data sheet ad5251/ad5252 rev. d document feedback information furnished by analog devices is belie ved to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no li cense is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 78 1.329.4700 ? 2004 C 2012 analog devices, inc. all rights reserved. technical support www.analog.com f eatures ad5251: dual 64 - position resolution ad5252: dual 256 - position resolution 1 k? , 10 k ? , 50 k ? , 100 k ? nonvolatile memory 1 stores wiper setting w/write protection power - on refreshed with eemem settings in 300 s typ eemem rewrite time = 540 s typ re sistance tolerance stored in nonvolatile memory 12 extra bytes in eemem for user - defined information i 2 c - compatible serial interface direct read/write access of rdac 2 and eemem registers predefined linear increment/decrement commands predefined 6 db step change commands synchronous or asynchronous dual - channel update wiper setting read back 4 mhz bandwidth 1 k? version single supply 2.7 v to 5.5 v dual supply 2.25 v to 2.75 v 2 slave address decoding bits allow operation of 4 devices 100- year typical data retention , t a = 55c op erating temperature: C 40c to +10 5c a pplications mechanical potentiometer replac ement general - purpose dac replacement lcd panel v com adjustment white led brightness adjustment rf base station power amp bias control programmable gain and offset control programmable voltage - to - current conversion programmable power supply sensor calibrat ions g eneral description the ad5251/ad5252 are dual - channel, i 2 c ? , nonvolatile mem - ory, digitally controlled potentiometers with 64/256 positions, respectively. these devices perform the same electronic adjust - ment functions as mechanical potentiometers, trimmers, and variable resistors. the parts versatile programmability allows multiple modes of operation, including read/write access in the rdac and eemem registers, increment/decrement of resistance, resistance changes in 6 db scales, wiper setting rea dback, and extra eemem for storing user - defined infor mation , such as memory data for other components, look - up table, or system identification information. f un ctional block diagram rdac1 regis- ter rdac3 regis- ter rdac1 rdac3 data control command decode logic address decode logic control logic ad5251/ ad5252 i 2 c serial interface power- on reset v dd a1 w1 b1 a3 w3 b3 v ss dgnd scl sda ad0 ad1 wp rdac eemem rab tol 03823-0-001 eemem power-on refresh figure 1. the ad5251/ad5252 allow the host i 2 c controllers to write any of the 64 - /256 - step wiper settings in the rdac registers and store them in the eemem. once the settings are stored, they are restored automatically to the rdac registers at system power - on; the settings can also be restored dynami cally. the ad5251/ad5252 provide additional increment, decrement, +6 db step change, and C 6 db step change in synchronous or asynchronous channel update mode. the increment and decrement functions allow stepwise linear adjustments, with a 6 db step chang e equivalent to doubling or halving the rdac wiper setting. these functions are useful for steep - slope, nonlinear adjustments , such as white led brightness and audio volume control. the ad5251/ad5252 have a patented resistance - tolerance storing function t hat allows the user to access the eemem and obtain the absolute end - to - end resistance values of the rdacs for precision applications. the ad5251/ad5252 are available in tssop - 14 packages in 1 k?, 10 k?, 50 k?, and 100 k? options. all parts are guaranteed to operate over the C 40c to + 105 c extended industrial temperature range. 1 the terms nonvolatile memory and eemem are used interchangeably. 2 the terms digital pote ntiometer and rdac are used interchangeably.
ad5251/ad5252 data sh eet rev. d | page 2 of 28 table o f contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 electrical characteristics ................................................................. 3 1 k? version .................................................................................. 3 10 k?, 50 k?, 100 k? versions .................................................. 5 interface timing characteristics ................................................ 7 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 10 i 2 c interface ..................................................................................... 14 i 2 c interface general description ............................................ 14 i 2 c interface detail description ............................................... 15 i 2 c - compatible 2 - wire serial bus ........................................... 20 theory of operation ...................................................................... 21 linear increment/decrement commands ............................. 21 6 db adjustments (doubling/halving wiper setting) ....... 21 digital input/output configuration ........................................ 22 multiple devices on one bus ................................................... 22 terminal voltage operation range ......................................... 22 power - up and power - down sequen ces .................................. 22 layout and power supply biasing ............................................ 23 digital potentiometer operation ............................................. 23 programmable rheostat operation ......................................... 23 programmable potentiometer operation ............................... 24 applications information .............................................................. 25 lcd panel v com adjustment .................................................... 25 current - sensing amplifier ....................................................... 25 adjustable high po wer led driver ........................................ 25 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 27 r evision history 9/12 rev. c to rev . d change d temperature range from C 40c to +8 5c to C 40c to +10 5c (throughout) .................................................................. 1 change d wp leakage current from 5 a to 8 a, table 1 ........ 4 change d wp leakage current from 5 a to 8 a, table 2 ........ 5 changes to fi gure 11 and figure 12 ............................................. 11 12/11 rev. b to rev. c changes to theory of operation section .................................... 21 changes to ordering guide .......................................................... 27 10 /09 rev. a to rev. b changes to figure 15 ...................................................................... 12 changes to figure 27 ...................................................................... 15 9 /05 rev. 0 to rev. a updated format .................................................................. universal change to figure 6 ......................................................................... 10 changes to figure 28 ...................................................................... 15 changes to figure 29 ...................................................................... 17 changes to rdac/eemem quick commands section .......... 1 8 changes to eemem write protection section .......................... 18 changes to figure 37 ...................................................................... 22 deleted table 13 and table 14 ...................................................... 23 change to figure 42 ....................................................................... 2 4 change to figure 46 ....................................................................... 2 5 changes t o ordering guide .......................................................... 2 7 6/04 revision 0: initial version
data sheet ad5251/ad5252 rev. d | page 3 of 28 electrical character istics 1 k ? version v dd = 3 v 10% or 5 v 10% , v ss = 0 v or v dd /v ss = 2.5 v 10% , v a = v dd , v b = 0 v, C 40c < t a < +10 5c, unless otherwise noted. table 1 . parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resolution n ad5251 6 bits ad5252 8 bits resistor differential nonlinearity 2 r - dnl r wb , r wa = nc, v dd = 5.5 v, ad5251 C 0.5 0.2 +0.5 lsb r wb , r wa = nc, v dd = 5.5 v, ad5252 C 1.00 0.25 +1.00 lsb r wb , r wa = nc, v dd = 2.7 v, ad5251 C 0.75 0.30 +0.75 lsb r wb , r wa = nc, v dd = 2.7 v, ad5252 C 1.5 0.3 +1.5 lsb resistor nonlinearity 2 r - inl r wb , r wa = nc, v dd = 5.5 v, ad5251 C 0.5 0.2 +0.5 lsb r wb , r wa = nc, v dd = 5.5 v, ad5252 C 2.0 0.5 +2.0 lsb r wb , r wa = nc, v dd = 2.7 v, ad5251 C 1.0 +2.5 +4.0 lsb r wb , r wa = nc, v dd = 2.7 v, ad5252 C 2 +9 +14 lsb nominal resistor tolerance r ab /r ab t a = 25c C 30 +30 % resistance temperature coefficient (r ab /r ab ) 10 6 /t 650 ppm/c wiper resistance r w i w = 1 v/r, v dd = 5 v 75 130 ? i w = 1 v/r, v dd = 3 v 200 300 ? channel - resistance matching r ab1 /r ab3 0.15 % dc characteristics potentiometer divider mode differential nonlinearity 3 dnl ad5251 C 0.5 0.1 +0.5 lsb ad5252 C 1.00 0.25 +1.00 lsb integral nonlinearity 3 inl ad5251 C 0.5 0.2 +0.5 lsb ad5252 C 2.0 0.5 +2.0 lsb voltage divider tempco (v w /v w ) 10 6 /t code = half scale 25 ppm/c full - scale error v wfse code = full scale, v dd = 5.5 v, ad5251 C 5 C 3 0 lsb code = full scale, v dd = 5.5 v, ad5252 C 16 C 11 0 lsb code = full scale, v dd = 2.7 v, ad5251 ?6 C 4 0 lsb code = full scale, v dd = 2.7 v, ad5252 C 23 C 16 0 lsb zero - scale error v wzse code = zero scale, v dd = 5.5 v, ad5251 0 3 5 lsb code = zero scale, v dd = 5.5 v, ad5252 0 11 16 lsb code = zero scale, v dd = 2.7 v, ad5251 0 4 6 lsb code = zero scale, v dd = 2.7 v, ad5252 0 15 20 lsb resistor terminals voltage range 4 v a , v b , v w v ss v dd v capacitance 5 a, b c a , c b f = 1 khz, me asured to gnd, code = half scale 85 pf capacitance 5 w c w f = 1 khz, measured to gnd, code = half scale 95 pf common - mode leakage current i cm v a = v b = v dd /2 0.01 1 a
ad5251/ad5252 data sh eet rev. d | page 4 of 28 parameter symbol conditions min typ 1 max unit digital inputs and outputs input logic high v ih v dd = 5 v, v ss = 0 v 2.4 v v dd /v ss = 2.7 v/0 v or v dd /v ss = 2.5 v 2.1 v input logic low v il v dd = 5 v, v ss = 0 v 0.8 v output logic high (sda) v oh r pull - up = 2.2 k? to v dd = 5 v, v ss = 0 v 4.9 v output logic low (sda) v ol r pull - up = 2.2 k? to v dd = 5 v, v ss = 0 v 0.4 v wp leakage current i wp wp = v dd 8 a a0 leakage current i a0 a0 = gnd 3 a input leakage current ( other than wp and a0) i i v in = 0 v or v dd 1 a input capacitance 5 c i 5 pf power supplies single - supply power range v dd v ss = 0 v 2.7 5.5 v dual - supply power range v dd /v ss 2.25 2.75 v positive supply current i dd v ih = v dd or v il = gnd 5 15 a negative supply current i ss v ih = v dd or v il = gnd, v dd = 2.5 v, v ss = C 2.5 v C 5 C 15 a eemem data storing mode current i dd_store v ih = v dd or v il = gnd 35 ma eemem data restoring mode cu rrent 6 i dd_restore v ih = v dd or v il = gnd 2.5 ma power dissipation 7 p diss v ih = v dd = 5 v or v il = gnd 0.075 mw power supply sensitivity pss v dd = 5 v 10% ?0.025 +0.010 +0.025 %/% v dd = 3 v 10% C 0.04 +0.02 +0.04 %/% dynamic characteristics 5 , 8 bandwidth C 3 db bw r ab = 1 k? 4 mhz total harmonic distortion thd v a = 1 v rms, v b = 0 v, f = 1 khz 0.05 % v w settling time t s v a = v dd , v b = 0 v 0.2 s resistor noise voltage e n_wb r wb = 500 ?, f = 1 k hz (thermal noise only) 3 nv / hz digital crosstalk c t v a = v dd , v b = 0 v, measure v w with adjacent rdac making full - scale change C 80 db analog coupling c at signal input at a1 and measure the output at w3, f = 1 khz C 72 db 1 typical values represent average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error (r - inl) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. r - dnl is the relative step change fr om an ideal value measured between successive tap positions. parts are guaranteed monotonic, except r - dnl of ad525 2 1 k? version at v dd = 2.7 v, i w = v dd /r for both v dd = 3 v and v dd = 5 v. 3 inl and dnl are measured at v w with the rdac configured as a potentiometer divider , similar to a voltage output digital - to - analog converter. v a = v dd and v b = 0 v. dnl s pecificatio n limits of 1 lsb maximum are guaranteed monotonic operating conditions. 4 resistor terminal a, terminal b, and terminal w have no limitations on polarity with respect to each other. 5 guaranteed by design and not subject to production test. 6 command 0 n op should be activated after command 1 to minimize i dd_read current consumption. 7 p diss is calculated from i dd v dd = 5 v . 8 all dynamic characteristics use v dd = 5 v.
data sheet ad5251/ad5252 rev. d | page 5 of 28 10 k ?, 50 k ?, 100 k ? versions v dd = +3 v 10% or +5 v 10% , v ss = 0 v or v dd /v ss = 2.5 v 10% , v a = v dd , v b = 0 v, C 40c < t a < +10 5c, unless otherwise noted. table 2 . parameter symbol conditions min typ 1 max unit dc charac teristics rheostat mode resolution n ad5251 6 bits ad5252 8 bits resistor differential nonlinearity 2 r - dnl r wb , r wa = nc, ad5251 ?0.75 0.10 +0.75 lsb r wb , r wa = nc, ad5252 ?1.00 0.25 +1.00 lsb resistor nonlinearity 2 r - inl r wb , r wa = nc, ad5251 ?0.75 0.25 +0.75 lsb r wb , r wa = nc, ad5252 ?2.5 1.0 +2.5 lsb nominal resistor tolerance r ab /r ab t a = 25c ?20 +20 % resistance temperature coefficient (r ab /r ab ) 10 6 /t 650 ppm/c wiper resistance r w i w = 1 v/r, v dd = 5 v 75 130 ? i w = 1 v/r, v dd = 3 v 200 300 ? channel - resistance matching r ab1 /r ab2 r ab = 10 k?, 50 k? 0.15 % r ab = 100 k? 0.05 % dc characteristics potentiometer divider mode differential nonlinearity 3 dnl ad5251 ?0.5 0.1 +0.5 lsb ad5252 ?1.0 0.3 +1.0 lsb integral nonlinearity 3 inl ad5251 ?0.50 0.15 +0.50 lsb ad5252 ?1.5 0.5 +1.5 lsb voltage divider temperature coefficient (v w /v w ) 10 6 /t code = half scale 15 ppm/ c full - scale error v wfse code = full scale, ad5251 ?1.0 ?0.3 0 lsb code = full scale, ad5252 ?3 ?1 0 lsb zero - scale error v wzse code = zero scale, ad5251 0 0.3 1.0 lsb code = zero scale, ad5252 0 1.2 3.0 lsb resistor terminals voltage rang e 4 v a , v b , v w v ss v dd v capacitance 5 a, b c a , c b f = 1 khz, measured to gnd, code = half scale 85 pf capacitance 5 w c w f = 1 khz, measured to gnd, code = half scale 95 pf common - mode leakage current i cm v a = v b = v dd /2 0.01 1.00 a digital inputs and outputs input logic high v ih v dd = 5 v, v ss = 0 v 2.4 v v dd /v ss = +2.7 v/0 v or v dd /v ss = 2.5 v 2.1 v input logic low v il v dd = 5 v, v ss = 0 v 0.8 v v dd /v ss = +2.7 v/0 v or v dd /v ss = 2.5 v 0 .6 v output logic high (sda) v oh r pull - up = 2.2 k? to v dd = 5 v, v ss = 0 v 4.9 v output logic low (sda) v ol r pull - up = 2.2 k? to v dd = 5 v, v ss = 0 v 0.4 v wp leakage current i wp wp = v dd 8 a a0 leakage curr ent i a0 a0 = gnd 3 a input leakage current (other than wp and a0) i i v in = 0 v or v dd 1 a input capacitance 5 c i 5 pf
ad5251/ad5252 data sh eet rev. d | page 6 of 28 parameter symbol conditions min typ 1 max unit power supplies single - supply pow er range v dd v ss = 0 v 2.7 5.5 v dual - supply power range v dd /v ss 2.25 2.75 v positive supply current i dd v ih = v dd or v il = gnd 5 15 a negative supply current i ss v ih = v dd or v il = gnd, v dd = 2.5 v, v ss = ?2.5 v ?5 ?15 a eemem data storing mode current i dd_store v ih = v dd or v il = gnd, t a = 0c to 10 5c 35 ma eemem data restoring mode current 6 i dd_restore v ih = v dd or v il = gnd, t a = 0c to 10 5c 2.5 ma power dissipation 7 p diss v ih = v dd = 5 v or v il = gnd 0.075 mw power supply sensitivity pss v dd = 5 v 10% ?0.005 +0.002 +0.005 %/% v dd = 3 v 10% ?0.010 +0.002 +0.010 %/% dynamic characteristics 5 , 8 C 3 db bandwidth bw r ab = 10 k?/50 k?/100 k? 400/80/ 40 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.05 % v w settling time t s v a = v dd , v b = 0 v, r ab = 10 k?/50 k?/100 k? 1.5/7/14 s resistor noise voltage e n_wb r ab = 10 k?/50 k?/100 k?, code = midscale, f = 1 kh z (thermal noise only) 9/20/29 nv / hz digital crosstalk c t v a = v dd , v b = 0 v, measure v w with adjacent rdac making full - scale change ?80 db analog coupling c at signal input at a1 and measure output at w3, f = 1 khz ?72 db 1 typical values represent average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error (r - inl) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. r - dnl is the relative step change from an ideal value measured between successive tap positions. parts are guaranteed mono tonic, except r - dnl of ad5252 1 k? version at v dd = 2.7 v, i w = v dd /r for both v dd = 3 v and v dd = 5 v. 3 inl and dnl are measured at v w with the rdac configured as a potentiometer divide r, similar to a voltage output d a c . v a = v dd and v b = 0 v. dnl s pecification limits of 1 lsb maxim um are guaranteed monotonic operating conditions. 4 resistor terminal a, terminal b, and terminal w have no limitations on polarity with respect to each other. 5 guaranteed by design and not subject to production test. 6 command 0 nop should be activated after command 1 to minimize i dd_read current consumption. 7 p diss is calculated from i dd v dd = 5 v . 8 all dynamic characteristics use v dd = 5 v.
data sheet ad5251/ad5252 rev. d | page 7 of 28 interface timing cha racteristics all input control voltages are specified with t r = t f = 2.5 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. switching characteristics are measured using both v dd = 3 v and 5 v. table 3 . interface timing and eemem reliability characteristics (all parts) 1 parameter symbol conditions min typ max unit interface timing scl clock frequency f scl 400 khz t buf bus - free time between stop and start t 1 1.3 s t hd;sta hold time (repeated start) t 2 after this period, the first clock pulse is generated. 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 s t su;sta set - up time for start condition t 5 0.6 s t hd; dat data hold time t 6 0 0.9 s t su;dat data set - up time t 7 100 ns t f fall time of both sda and scl signals t 8 300 ns t r rise time of both sda and scl signals t 9 300 ns t su;sto set - up time for stop condition t 10 0.6 s eemem data storing time t eemem_store 26 m s eemem data restoring time at power - on 2 t eemem_restore1 v dd rise time dependent. measure without decoupling capacitors at v dd and v ss . 300 s eemem data restoring time upon restore command or reset operation 2 t eemem_r estore2 v dd = 5 v . 300 s eemem data rewritable time (delay time after power - on or reset before eemem can be written) t eemem_rewrite 540 s flash/ee memory reliability endurance 3 100 k cycles data retention 4 100 years 1 guaranteed by design; not subject to production test. see figure 23 for location of measured values. 2 during power - up, all outputs are preset to midscale before restoring the eemem contents. rdac0 has the shortest eemem data restoring time, whereas rdac3 has the longest. 3 e ndurance is qualified to 100,000 cycles per jedec standard 2 2, method a117 , and measured at ? 40 c, +25 c, and + 10 5 c; typical endurance at +25 c is 700,000 cycles. 4 retention lifetime equivalent at junction temperature t j = 55c per jedec std. 22, method a117. retention lifetime based on an activation energy of 0.6 ev derates with junction tempe rature in flash/ee memory .
ad5251/ad5252 data sh eet rev. d | page 8 of 28 absolute max imum ratings t a = 25c, unless otherwise noted. table 4 . parameter rating v dd to gnd ?0.3 v, +7 v v ss to gnd +0.3 v, ?7 v v dd to v ss 7 v v a , v b , v w to gnd v ss , v dd maximum current i wb , i wa pulsed 20 ma i wb continuous (r wb 1 k?, a open) 1 5 ma i wa continuous (r wa 1 k?, b open) 1 5 ma i ab continuous (r ab = 1 k?/10 k?/50 k?/100 k?) 1 5 ma/500 a/ 100 a/50 a digital inputs and output voltage to g nd 0 v, 7 v operating temperature range ?40c to +10 5c maximum junction temperature (t jmax ) 150c storage temperature range ?65c to +150c lead temperature (soldering, 10 sec) 300c vapor phase (60 sec) 215c infrared (15 sec) 220c tssop - 14 therm al resistance 2 ja 136c/w 1 max imum terminal current is bound by the maximum ap plied voltage across any two of the a, b, and w terminals at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package. v dd = 5 v. 2 package p ower dissipation = (t jmax ? t a )/ ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in t he operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet ad5251/ad5252 rev. d | page 9 of 28 pin configuration an d function descripti ons 1 2 3 4 5 6 7 ad0 wp w1 sda a1 b1 v dd 14 1 3 1 2 1 1 1 0 9 8 b3 a3 ad1 v ss scl dgnd w3 03823-0-002 ad5251/ ad5252 top view (not to scale) figure 2 . pin configuration table 5 . pin function descriptions pin o. mnemonic description 1 v dd positive power supply pin. connect +2.7 v to +5 v for single supply or 2.7 v for dual supply, where v dd C v ss 5.5 v. v dd must be able to source 35 ma for 26 ms when storing data to eemem. 2 ad0 i 2 c device address 0. ad0 and ad1 allow four ad5251/ad5252 device s to be addressed. 3 wp write protect, active low. v wp v dd + 0.3 v. 4 w1 wipe r terminal of rdac1. v ss v w1 v dd . 1 5 b1 b terminal of rdac1. v ss v b1 v dd . 1 6 a1 a terminal of rdac1. v ss v a1 v dd . 1 7 sda serial data input/output pin. shifts in one bit at a time upon positive clock edges. msb loaded first. open - drain mosfet requires pull - up resistor. 8 v ss negative supply. connect to 0 v for single supply or C 2.7 v for dual supply, where v dd C v ss + 5.5 v. if v ss is used in dual supply, v ss must be able to sink 35 ma for 26 ms when storing data to eemem. 9 scl serial input register clock pin. shifts in one bit at a time upon positive clock edges. v scl ( v dd + 0.3 v). pull - up resistor is recommended for scl to ensure minimum power. 10 dgnd digital ground. connect to system analog ground at a single point. 11 ad1 i 2 c device address 1. ad0 and ad1 allow four ad5251/ad5252 device s to be addressed. 12 a3 a terminal of rdac3. v ss v a3 v dd . 1 13 b3 b terminal of rdac3. v ss v b3 v dd . 1 14 w3 wiper terminal of rdac3. v ss v w3 v dd . 1 1 for quad - channel device software compa tibility , the dual potentiometers in the parts are designated as rdac1 and rdac3.
ad5251/ad5252 data sh eet rev. d | page 10 of 28 typical performance characteristics r-inl (lsb) code (decimal) 03823-0-015 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 32 64 96 128 160 192 224 256 t a = ?40c, +25c, +85c, +125c figure 3. r - inl vs. code r-dnl (lsb) code (decimal) 03823-0-016 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 32 64 96 128 160 192 224 256 t a = ?40c, +25c, +85c, +125c figure 4. r - dnl vs. code inl (lsb) code (decimal) 03823-0-017 ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 0 32 64 96 128 160 192 224 256 t a = ?40c, +25c, +85c, +125c figure 5 . inl vs. code dnl (lsb) code (decimal) 03823-0-018 ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 0 32 64 96 128 160 192 224 256 t a = ? 40 c, +25 c, +85 c, +125 c figure 6 . dnl vs. code i dd (a) temperature (c) 03823-0-019 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?40 ?20 0 20 40 60 80 100 120 i dd @ v dd = 5.5v i dd @ v dd = 2.7v i ss @ v dd = 2.7v, v ss = ?2.7v figure 7 . supply current vs. temperature digital input voltage (v) 03823-0-020 0.0001 0.01 0.001 0.1 1 10 0 1 2 3 4 5 6 v dd = 5.5v v dd = 2.7v i dd (ma) figure 8 . supply current vs. d igital input voltage, t a = 25c
data sheet ad5251/ad5252 rev. d | page 11 of 28 r wb ( ? ) v bias (v) 03823-0-021 20 0 40 60 80 100 120 140 160 200 240 180 220 1 0 23456 v dd = 2.7v t a = 25 ?c v dd = 5.5v t a = 25 ?c data = 0x00 figure 9. wiper resistance vs. v bias temperature (?c) 03823-0-022 ?6 ?4 ?2 0 2 4 6 ?40 ?20 0 20 40 60 80 100 120 ? r wb (%) figure 10. change of r wb vs. temperature 03823-0-023 code (decimal) 0 326496128160 10k ? 100k ? 50k ? 192 224 256 rheostat mode tempco (ppm/c) v dd =5v t a = ?40c to +85c v a =v dd v b =0v 500 550 600 650 700 750 800 850 900 950 1000 figure 11. ad5252 rheostat mode tempco ?r wb /?t vs. code 03823-0-024 code (decimal) 0 20 25 10 5 15 30 35 40 45 50 0 32 64 96 128 160 192 224 256 potentiometer mode tempco (ppm/c) 100k ? 50k ? 10k ? v dd = 5v t a = ?40c to +85c v a = v dd v b = 0v figure 12. ad5252 potentiometer mode tempco ?v wb /?t vs. code ?60 ?48 ?24 ?12 0 ?36 ?54 ?30 ?18 ?6 ?42 gain (db) 1k 10k 10 100 100k 1m 10m frequency (hz) 03823-0-025 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x00 figure 13. ad5252 gain vs. frequency vs. code, r ab = 1 k, t a = 25c ?60 ?48 ?24 ?12 0 ?36 ?54 ?30 ?18 ?6 ?42 gain (db) 1k 10k 10 100 100k 1m 10m frequency (hz) 03823-0-026 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x00 figure 14. ad5252 gain vs. frequency vs. code, r ab = 10 k , t a = 25c
ad5251/ad5252 data sheet rev. d | page 12 of 28 ?60 ?48 ?24 ?12 0 ?36 ?54 ?30 ?18 ?6 ?42 gain (db) 1k 10k 10 100 100k 1m 10m frequency (hz) 03823-0-027 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x00 figure 15. ad5252 gain vs. frequency vs. code, r ab = 50 k , t a = 25c ?60 ?48 ?24 ?12 0 ?36 ?54 ?30 ?18 ?6 ?42 gain (db) 1k 10k 10 100 100k 1m 10m frequency (hz) 03823-0-028 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x00 figure 16. ad5252 gain vs. frequency vs. code, r ab = 100 k , t a = 25c ? r ab ( ? ) code (decimal) 03823-0-029 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 0 32 64 96 128 160 192 224 256 100k ? 1k ? 10k ? v dd = 5.5v 50k ? figure 17. ad5252 r ab vs. code, t a = 25c clock frequency (hz) 03823-0-030 0 0.6 0.4 0.2 0.8 1.0 1.2 1 100 10 1k 10k 100k 1m 10m v dd = 2.7v t a = 25c v dd = 5.5v i dd (ma) figure 18. supply current vs. digital input clock frequency 03823-0-031 digital feedthrough clk v dd = 5v v w 400ns/div figure 19. clock feedthrough and midscale transition glitch 03823-0-032 v wb1 (0x3f stored in eemem) v wb3 (0x3f stored in eemem) v dd = va1 = va3 = 3.3v gnd = vb1 = vb3 midscale preset restore rdac1 setting to 0x3f restore rdac3 setting to 0x3f v dd (no de- coupling caps) midscale preset figure 20. t eemem_restore of rdac0 and rdac3
data sheet ad5251/ad5252 rev. d | page 13 of 28 code (decimal) 03823-0-033 0 3 2 1 4 5 6 0 8 16 24 32 40 48 56 64 theoretical i wb_max (ma) r ab = 1k ? v a = v b = open t a = 25 c r ab = 10k ? r ab = 50k ? r ab = 100k ? figure 21 . ad5251 i wb_max vs. code code (decimal) 03823-0-034 0 3 2 1 4 5 6 0 32 64 96 128 160 192 224 256 theoretical i wb_max (ma) r ab = 1k ? v a = v b = open t a = 25 c r ab = 10k ? r ab = 50k ? r ab = 100k ? figure 22 . ad5252 i wb_max vs. code
ad5251/ad5252 data sheet rev. d | page 14 of 28 i 2 c interface 03823-0-003 t 1 t 2 t 3 t 8 t 8 t 9 t 9 t 6 t 4 t 7 t 5 t 2 t 10 ps s scl sd a p figure 23. i 2 c interface timing diagram i 2 c interface general description r/w a/a s slave address (7-bit) a 0 write a instructions (8-bit) data transferred (n bytes + acknowledge) data (8-bit) p 03823-0-004 from master to slave from slave to master s = start condition p = stop condition a = acknowledge (sda low) a = not acknowledge (sda high) r/w = read enable at high and write enable at low figure 24. i 2 cmaster writing data to slave r/w a s slave address (7-bit) 1 read data transferred (n bytes + acknowledge) data (8-bit) data (8-bit) p 03823-0-005 a a figure 25. i 2 cmaster reading data from slave r/w r/w s slave address (7-bit) read or write (n bytes + acknowledge) slave address data a s 03823-0-006 repeated start read or write direction of transfer may change at this point a a/a (n bytes + acknowledge) data p a/a figure 26. i 2 ccombined write/read
data sheet ad5251/ad5252 rev. d | page 15 of 28 i 2 c interface detail d escription 0 write 03823-0-007 s 0 1 0 1 1 a d 1 a d 0 0 a a 4 a 3 a 2 a 1 a 0 a p d at a 0 (1 byte + acknowledge) sl a ve address instructions and address cmd/ reg ee/ rdac 0 reg a/ a from master t o sl a ve from sl a ve t o master s = s t art condition p = s t o p condition a = acknowledge (sd a low) a = not acknowledge (sd a high) r/w = read enable a t high and write enable a t low cmd/reg = command enable bi t , logic high/register access bi t , logic low ee/rdac = eemem register, logic high/rdac register, logic low a4, a3, a2, a1, a0 = rdac/eemem register addresses figure 27 . single write mode 0 write 03823-0-008 s 0 1 0 1 1 a d 1 a d 0 0 a a 4 a 3 a 2 a 1 a 0 p a a rdac1 data rdac3 data 0 (n bytes + acknowledge) rdac slave address rdac instructions and address cmd/ reg ee/ rdac 0 reg a/ a a x data figure 28 . consecutive write mode table 6 . addresses for writing data by te contents to rdac registers (r/ w = 0, cmd/ reg = 0, ee/ rdac = 0) a4 a3 a2 a1 a0 rdac data byte description 0 0 0 0 0 reserved 0 0 0 0 1 rdac1 6 -/8 - bit wiper setting (2 msb of ad5251 a re x) 0 0 0 1 0 reserved 0 0 0 1 1 rdac3 6 -/8 - bit wiper setting (2 msb of ad5251 are x) 0 0 1 0 0 reserved : : : : : : : : : : : : 0 1 1 1 1 reserved
ad5251/ad5252 data sh eet rev. d | page 16 of 28 rdac/eemem write setting the wiper position requires an rdac write operation. the single w rite operation is shown in figure 27 , and the consecutive write operation is shown in figure 28 . in the consecutive write operation, if the rdac is selected and the address starts at 00001, the first data byte goes to rdac1 and the second data byte goes to rdac3. the rdac address is shown in table 6 . while the rdac wiper setting is controlled by a specific rdac register, each rdac register corresponds to a specific eemem location, which provides nonvolatile wiper storage functionality. the addresses are shown in table 7 . the single and consecutive write operations also apply to eemem write operations. there are 12 nonvolatile me mory locations: eemem4 to eemem15. users can store a total of 12 bytes of information, such as memory data for other components, look - up tables, or system identification information. in a write operation to the eemem registers, the device disables the i 2 c interface during the internal write cycle. acknowledge polling is required to determine the completion of the write cycle. see the eemem write - acknowledge polling section. rdac/eemem read the ad5251/ad5252 provide two different r dac or eemem read operations. for example, figure 29 shows the method of reading the rdac0 to rdac3 contents without specifying the address, assuming address rdac0 was already selected in the previous operation. if an rdac_n addr ess other than rdac0 was previously selected, readback starts with address n, followed by n + 1, and so on. figure 30 illustrates a random rdac or eemem read operation. this operation allows users to specify which rdac or eemem register is read by issuing a dummy write command to change the rdac address pointer and then proceeding with the rdac read operation at the new address location. table 7 . addresses for writing (storing) rdac settings and use r - defined data to eemem registers (r/ w = 0, cmd/ reg = 0, ee/ rdac = 1) a4 a3 a2 a1 a0 data byte descrition 0 0 0 0 0 reserved 0 0 0 0 1 store rdac1 setting to eemem1 1 0 0 0 1 0 reserv ed 0 0 0 1 1 store rdac3 setting to eemem3 1 0 0 1 0 0 store user data to eemem4 0 0 1 0 1 store user data to eemem5 0 0 1 1 0 store user data to eemem6 0 0 1 1 1 store user data to eemem7 0 1 0 0 0 store user data to eemem8 0 1 0 0 1 store user data to eemem9 0 1 0 1 0 store user data to eemem10 0 1 0 1 1 store user data to eemem11 0 1 1 0 0 store user data to eemem12 0 1 1 0 1 store user data to eemem13 0 1 1 1 0 store user data to eemem14 0 1 1 1 1 store user data to eemem15 1 users can store any of the 64 rdac settings directly to the eemem for ad5251, or any of the 256 rdac settings directly to the eemem for the ad5252. this is not limited to current rdac wiper setting . table 8 . addr esses for reading (restoring) rdac settings and user data from eemem (r/ w = 1, cmd/ reg = 0, ee/ rdac = 1) a4 a3 a2 a1 a0 data byte descrition 0 0 0 0 0 reserved 0 0 0 0 1 read rdac1 s etting from eemem1 0 0 0 1 0 reserved 0 0 0 1 1 read rdac3 setting from eemem3 0 0 1 0 0 read user data from eemem4 0 0 1 0 1 read user data from eemem5 0 0 1 1 0 read user data from eemem6 0 0 1 1 1 read user data from eemem7 0 1 0 0 0 read user da ta from eemem8 0 1 0 0 1 read user data from eemem9 0 1 0 1 0 read user data from eemem10 0 1 0 1 1 read user data from eemem11 0 1 1 0 0 read user data from eemem12 0 1 1 0 1 read user data from eemem13 0 1 1 1 0 read user data from eemem14 0 1 1 1 1 read user data from eemem15
data sheet ad5251/ad5252 rev. d | page 17 of 28 1 read 03823-0-009 s 0 1 0 1 1 a d 1 a d 0 1 a p a rdac1 eemem or register data rdac3 eemem or register data slave address (n bytes + acknowledge) a/ a a x data figure 29 . rdac current read (restricted to previously selected address stored in the register) p s slave address 0 write slave address instruction and address a 1 s 03823-0-010 repeated start 1 read a 0 a (n bytes + acknowledge) rdac or eemem data a/a figure 30 . rdac or eemem random read 0 write 03823-0-011 1 cmd s 0 1 0 1 1 a d 1 a d 0 0 a c 3 c 2 c 1 c 0 a 2 a 1 a 0 a p rdac slave address cmd/ reg from master to slave from slave to master s = start condition p = stop condition a = acknowledge (sda low) a = not acknowledge (sda high) ad1, ad0 = i 2 c device address bits; must match with the logic states at pins ad1, ad0 r/w = read enable bit, logic high/write enable bit, logic low cmd/reg = command enable bit, logic high/register access bit, logic low c3, c2, c1, c0 = command bits a2, a1, a0 = rdac/eemem register addresses figure 31 . rdac quick command write (dummy write)
ad5251/ad5252 data sh eet rev. d | page 18 of 28 rdac/eemem quick commands the ad5251/ad5252 feature 12 quick commands that facilitate easy manipulation of rdac wiper settings and provide rdac - to - eemem storing and restoring functions. the command format is shown in figure 31 , and the command descriptions are shown in table 9 . when using a quick command, issuing a third byte is not needed, but is allowed. the quick commands reset and store rdac to eeme m require acknowledge polling to determine whether the command has finished executing. r ab tolerance stored in read - only memory the ad5251/ad5252 feature patented r ab tolerances storage in the nonvolatile memory. the tolerance of each channel is stored in the memory during the factory production and can be read by users at any time. the knowledge of the stored tolerance, which is the average of r ab over all codes (see figure 16 ), allows users to predict r ab accurately. this featur e is valuable for precision, rheostat mode, and open - loop applications in which knowledge of absolute resistance is critical. the stored tolerances reside in the read - only memory and are expressed as percentage s . each tolerance is stored in two memory loca tions (see table 10 ). the tolerance data is expressed in sign magnitude binary format stored in two bytes; an example is shown in figure 32. for the first byte in r egister n, the msb is designated for the sign (0 = + and 1 = C ) and the 7 lsb is designated for the integer portion of the tolerance. for the second byte in r egister n + 1, all eight data bits are designated for the decimal portion of tolerance. as shown in table 10 and figure 32 , for example, if the rated r ab is 10 k? and the data readback from address 11000 shows 0001 1100 and address 11001 shows 0000 1111, then rdac0 tolerance can be calculated as msb: 0 = + next 7 msb: 001 1100 = 28 8 lsb: 0000 1111 = 15 2 C 8 = 0.06 tolerance = 28.06% and, therefore, r ab_actual = 12.806 k? eemem write - acknowledge polling after each write operation to the eemem registers, an internal write cycle begins. the i 2 c interface of the device i s disabled. to determine if the internal write cycle is complete and the i 2 c interface is enabled, interface polling can be executed. i 2 c interface polling can be conducted by sending a start condition , followed by the slave address and the write bit. if t he i 2 c interface responds with an ack, the write cycle is complete and the interface is ready to proceed with further operations. other - wise, i 2 c interface polling can be repeated until it succeeds. command 2 and command 7 also require acknowledge polling. eemem write protection setting the wp pin to logic low after eemem programming protects the memory and rdac registers from future write operations. in this mode, the eemem and rdac read operations function as normal. table 9 . rdac -to - eemem interface and rdac operation quick command bits (cmd/ reg = 1, a2 = 0) c3 c2 c1 c0 command description 0 0 0 0 nop 0 0 0 1 restore eemem (a1, a0) to rdac (a1, a0) 1 0 0 1 0 store rdac (a1, a0) to ee mem (a1, a0) 0 0 1 1 decrement rdac (a1, a0) 6 db 0 1 0 0 decrement all rdacs 6 db 0 1 0 1 decrement rdac (a1, a0) one step 0 1 1 0 decrement all rdacs one step 0 1 1 1 reset: restore eemems to all rdacs 1 0 0 0 increment rdacs (a1, a0) 6 db 1 0 0 1 increment all rdacs 6 db 1 0 1 0 increment rdacs (a1, a0) one step 1 0 1 1 increment all rdacs one step 1 1 0 0 reserved : : : : : : : : : : 1 1 1 1 reserved 1 this command leaves the device in the eemem r ead power state , which consumes power. i ssue the nop comman d to return the device to its idle state.
data sheet ad5251/ad5252 rev. d | page 19 of 28 table 10 . address table for reading tolerance (cmd/ reg = 0, ee/ rdac = 1, a4 = 1) a4 a3 a2 a1 a0 data byte description 0 0 0 0 0 reserved : : : : : : : : : : : : 1 1 0 0 1 reserved 1 1 0 1 0 sign and 7 - bit integer values of rdac1 tolerance (read only) 1 1 0 1 1 8 -bi t decimal value of rdac1 tolerance (read only) 1 1 1 0 0 reserved 1 1 1 0 1 reserved 1 1 1 1 0 sign and 7 - bit integer values of rdac3 tolerance (read only) 1 1 1 1 1 8 - bit decimal value of rdac3 tolerance (read only) 03823-0-012 a a a d7 d6 d5 d4 d3 d2 d1 d0 sign sign 7 bits for integer number 2 6 2 5 2 4 2 3 2 2 2 1 2 0 d7 d6 d5 d4 d3 d2 d1 d0 8 bits for decimal number 2 ? 8 2 ? 1 2 ? 2 2 ? 3 2 ? 4 2 ? 5 2 ? 6 2 ? 7 figure 32 . format of stored tolerance in sign magnitude format with bit position descriptions (unit is percent, only data bytes are sh own)
ad5251/ad5252 data sh eet rev. d | page 20 of 28 i 2 c - compatible 2 - wire serial bus sda frame 1 slave address byte frame 2 instruction byte scl ack. by ad525x ack. by ad525x ack. by ad525x frame 1 data byte stop by master 03823-0-013 start by master 0 1 1 0 1 1 ad1 ad0 r/w x x x x x x x x d7 d6 d5 d4 d3 d2 d1 d0 9 1 9 1 9 figure 33 . general i 2 c write pattern 03823-0-014 sda frame 1 slave address byte frame 2 rdac register scl ack. by ad525x no ack. by master stop by master start by master 0 1 1 0 1 1 ad1 ad0 d7 d6 d5 d4 d3 d2 d1 d0 9 1 9 r/w figure 34 . general i 2 c read pattern the first byte of the ad5251/ad5252 is a slave address byte (see figure 33 and figure 34 ). it has a 7 - bit slave address and an r/ w bit. the 5 m sb of the slave address is 01011, and the next 2 lsb is determined by the states of the ad1 and ad0 pins. ad1 and ad0 allow the user to place up to four ad5251/ad5252 device s on one bus. ad5251/ad5252 can be controlled via an i 2 c - compatible serial bus and are connected to this bus as slave devices. the 2 - wire i 2 c serial bus protocol (see figure 33 and figure 34 ) follows: 1. the master initiates a data transfer by establishing a start condition, such that s da goes from high to low while scl is high (see figure 33 ). the following byte is the slave address byte, which consists of th e 5 msb of a slave address defined as 01011. the next two bits are ad1 and ad0, i 2 c device address bits . depending on the states of their ad1 and ad0 bits, four ad5251/ad5252 device s can be addressed on the same bus. the last lsb, the r/ w bit, determines whether data is read from or written to the slave device. the slave whose address corr esponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is called an acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. 2. in the write mode (except when restoring eemem to the rdac register), there is an instruction byte that follows the slave address byte. the msb of the instruction byte is labeled cmd/ reg . msb = 1 enabl es cmd, the command instruction byte; msb = 0 enables general register writing. the third msb in the instruction byte, labeled ee/ rdac , is true when msb = 0 or when the device is in general writing mode. ee enables the eemem register , and reg enabl es the rdac register. the 5 lsb , a4 to a0, designate s the addresses of the eemem and rdac registers (see figure 27 and figure 28 ). when msb = 1 or when the device is in cmd mode, the four bits following the msb are c3 to c1, which correspond to 12 predefined eemem controls and quick commands; there are also four facto ry - reserved commands. the 3 lsb a2, a1, and a0 are addresses, but only 001 and 011 are used for rdac1 and rdac3, respectivel y (see figure 31 ). after acknowledging the instruction byte, the last byte in the write mode is the data byte. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledg e bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 33 ). 3. in current read mode, the rdac0 data byte immediately follows the acknowledgment of t he slave address byte. after an acknowledgement, rdac1 follows, then rdac2, and so on. (there is a slight difference in write mode, where the last eight data bits representing rdac3 data are f ollowed by a no acknowledge bit.) similarly, the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 34 ). another reading method, random read method, is shown in figure 30. 4. when all data bit s have been read or written, a stop condition is established by the master. a stop condition is defined as a low - to - high transition on the sda line that occurs while scl is high. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition (see figure 33 ). in read mode, the master issues a no acknowledge for the ninth clock pulse, that is, the sda line remains high. the master brings the sda line low before the 10 th clock pulse and th en brings the sda line high to establish a stop condition (see figure 34).
data sheet ad5251/ad5252 rev. d | page 21 of 28 theory of operation the ad5251/ad5252 are dual - channel digital potentiometers in 1 k ? , 10 k ? , 50 k ? , or 100 k ? that allow 64/256 linear resistance step adjustments. the ad5251/ad5252 employ double - gate cmos eeprom technology, which allows resistance settings and user - defined data to be stored in the eemem registers. the eemem is nonvolati le, such that settings remain when power is removed. the rdac wiper settings are restored from the nonvolatile memory settings during device power - up and can also be restored at any time during operation. the ad5251/ad5252 resistor wiper positions are det ermined by the rdac register contents. the rdac register acts like a scratch - pad register, allowing unlimited changes of resistance settings. rdac register contents can be changed using the devices serial i 2 c interface. the format of the data - words and th e commands to program the rdac registers are discussed in the i 2 c interface detail description section. the four rdac registers have corresponding eemem memory locations that provide nonvolatile storage of resistor wiper position settings. the ad5251/ad5252 provide commands to store the rdac register contents to their respective eemem memory locations. during subsequent power - on sequences, the rdac registers are automatically loaded with the stored value. whenever the eemem write operation is enabled, the device activates the internal charge pump and raises the eemem cell gate bias voltage to a high level; this essentially erases the current content in the eemem register and allows subsequent storage of the new content. saving data to an eemem register consumes about 35 ma of current and lasts approximately 26 ms. because of charge - pump operation, all rdac channels may experience noise coupling during the eemem writing operation. the eemem restore time in power - up or during operatio n is about 300 s. note that the power - up eemem refresh time depends on how fast v dd reaches its final value. as a result, any supply voltage decoupling capacitors limits the eemem restore time during power - up. for example, figure 20 shows a power - up profile of the v dd where there is no decoupling capacitor and the applied power is a digital signal. the device initially resets the m easured rdacs to midscale before restoring the eemem contents . by default, eemem is loaded at midsca le until a new value is loaded. the omission of the decoupling capacitors should only be considered when the fast restoring time is absolutely needed in the applica tion. in addition, users should issue a nop command 0 immediately after using command 1 to r estore the eemem setting to rdac, thereby minimizing supply current dissipation. reading user data directly from eemem does not require a similar nop command execution. in addition to the movement of data between rdac and eemem registers, the ad5251/ad5252 provide other shortcut commands that facilitate programming, as shown in table 11. table 11 . quick commands command description 0 n o p. 1 restore eemem content to rdac. user s should issue nop immediately after this command to conserve power. 2 store rdac register setting to eemem. 3 decrement rdac 6 db (shift data bits right). 4 decrement all rdacs 6 db (shift all data bits right). 5 decrement rdac one step. 6 decrement all rdacs one step. 7 reset e emem contents to all rdacs. 8 increment rdac 6 db (shift data bits left). 9 increment all rdacs 6 db (shift all data bits left). 10 increment rdac one step. 11 increment all rdacs one step. 12 to 15 reserved. linear increment/dec rement commands the increment and decrement commands (10, 11, 5, and 6) are useful for linear step - adjustment applications. these commands simplify microcontroller software coding by allowing the controller to send just an increment or decrement command to the ad5251/ad5252. the adjustments can be directed to a single rdac or to all four rdacs. 6 d b adjustments (doubling/halving wi per setting) the ad5251/ad5252 accommodate 6 db adjustments of the rdac wiper positions by shifting the register contents to left/right for incr ement/decrement operations, respectively. command 3, command 4, command 8, and command 9 can be used to increment or decrement the wiper positions in 6 db steps synchronously or asynchronously. incrementing the wiper position by +6 db essentially doubles t he rdac register value, whereas decrementing the wiper position by C 6 db halves the register content. internally, the ad5251/ad5252 use shift registers to shift the bits left and right to achieve a 6 db increment or decrement. the maximum number of adjust ments is nine and eight steps for increment ing from zero scale and decrement ing from full scale, respectively. these functions are useful for various audio/video level adjustments, especially for white led brightness settings in which human visual response s are more sensitive to large adjustments than to small adjustments .
ad5251/ad5252 data sheet rev. d | page 22 of 28 digital input/outp ut configuration sda is a digital input/output with an open-drain mosfet that requires a pull-up resistor for proper communication. on the other hand, scl and wp are digital inputs for which pull-up resistors are recommended to minimize the mosfet cross- conduction current when the driving signals are lower than v dd . scl and wp have esd protection diodes, as shown in figure 35 and figure 36. wp can be permanently tied to v dd without a pull-up resistor if the write-protect feature is not used. if wp is left floating, an internal current source pulls it low to enable write protection. in applications in which the device is programmed infrequently, this allows the part to default to write-protection mode after any one-time factory programming or field calibration without using an on-board pull-down resistor. because there are protection diodes on all inputs, the signal levels must not be greater than v dd to prevent forward biasing of the diodes. 03823-0-035 gnd s cl v dd figure 35. scl digital input 03823-0-036 gnd inputs wp v dd figure 36. equivalent wp digital input multiple devices on one bus the ad5251/ad5252 are equipped with two addressing pins, ad1 and ad0, that allow up to four ad5251/ad5252 devices to be operated on one i 2 c bus. to achieve this result, the states of ad1 and ad0 on each device must first be defined. an example is shown in table 12 and figure 37. in i 2 c programming, each device is issued a different slave address01011(ad1)(ad0) to complete the addressing. table 12. multiple devices addressing ad1 ad0 device addressed 0 0 u1 0 1 u2 1 0 u3 1 1 u4 03823-0-037 5v r p r p 5v 5v 5v u1 ad0 ad1 sda scl master u2 ad0 ad1 sda scl u3 ad0 ad1 sda scl u4 ad0 ad1 sda sda scl scl figure 37. multiple ad5251/ad5252 devices on a single bus terminal voltage operation range the ad5251/ad5252 are designed with internal esd diodes for protection; these diodes also set the boundaries for the terminal operating voltages. positive signals present on te r m i n a l a , te r m i n a l b, or te r m i n a l w t h at e x c e e d v dd are clamped by the forward-biased diode. similarly, negative signals on te r m i n a l a , te r m i n a l b, or te r m i n a l w t h at are more negative than v ss are also clamped (see figure 38). in practice, users should not operate v ab , v wa , and v wb to be higher than the voltage across v dd to v ss , but v ab , v wa , and v wb have no polarity constraint. v ss v dd a w b 03823-0-018 figure 38. maximum terminal voltages set by v dd and v ss power-up and power-down sequences because the esd protection diodes limit the voltage compliance at te r m i n a l a , te r m i n a l b, a nd te r m i n a l w ( s e e fi g u re 3 8 ) , it i s important to power on v dd /v ss before applying any voltage to these terminals. otherwise, the diodes are forward biased such that v dd /v ss are powered unintentionally and may affect the users circuit. similarly, v dd /v ss should be powered down last. the ideal power-up sequence is in the following order: gnd, v dd , v ss , digital inputs, and v a /v b /v w . the order of powering v a , v b , v w , and the digital inputs is not important, as long as they are powered after v dd /v ss .
data sheet ad5251/ad5252 rev. d | page 23 of 28 layout and power supply biasing it is always a good practice to employ a compact, minimum lead-length layout design. the leads to the input should be as direct as possible, with a minimum conductor length. ground paths should have low resistance and low inductance. similarly, it is also good practice to bypass the power supplies with quality capacitors. low equivalent series resistance (esr) 1 f to 10 f tantalum or electrolytic capacitors should be applied at the supplies to minimize any transient disturbance and filter low frequency ripple. figure 39 illustrates the basic supply-bypassing configuration for the ad5251/ad5252. v dd v dd v ss v ss gnd c3 ad5251/ad5252 c4 c1 + + c2 10 ? f 10 ? f 0.1 ? f 0.1 ? f 03823-0-039 figure 39. power supply- bypassing configuration the ground pin of the ad5251/ad5252 is used primarily as a digital ground reference. to minimize the digital ground bounce, the ad5251/ad5252 ground terminal should be joined remotely to the common ground (see figure 39). digital potentiometer operation the structure of the rdac is designed to emulate the performance of a mechanical potentiometer. the rdac contains a string of resistor segments with an array of analog switches that act as the wiper connection to the resistor array. the number of points is the resolution of the device. for example, the ad5251/ad5252 emulate 64/256 connection points with 64/256 equal resistance, r s , allowing them to provide better than 1.5%/0.4% resolution. figure 40 provides an equivalent diagram of the connections between the three terminals that make up one channel of the rdac. switches sw a and sw b are always on, but only one of switches sw(0) to sw(2 n C 1 ) can be on at a time (determined by the setting decoded from the data bit). because the switches are nonideal, there is a 75 wiper resistance, r w . wiper resistance is a function of supply voltage and temperature: lower supply voltages and higher temperatures result in higher wiper resistances. consideration of wiper resistance dynamics is important in applications in which accurate prediction of output resistance is required. sw b sw(1) sw(0) b x r s r s sw a sw(2 n ? 1) a x w x sw(2 n ? 2) rdac wiper register and decoder r s = r ab /2 n r s digital c ircuitr y o mitted for c larit y 03823-0-040 figure 40. equivalent rdac structure programmable rheostat operation if either the w-to-b or w-to-a terminal is used as a variable resistor, the unused terminal can be opened or shorted with w; such operation is called rheostat mode (see figure 41). the resistance tolerance can range 20%. a w b 03823-0-041 a w b a w b figure 41. rheostat mode configuration the nominal resistance of the ad5251/ad5252 has 64/256 contact points accessed by the wiper terminal, plus the b terminal contact. the 6-/8-bit data-word in the rdac register is decoded to select one of the 64/256 settings. the wipers first connection starts at the b terminal for data 0x00. this b terminal connection has a wiper contact resistance, r w , of 75 , regardless of the nominal resistance. the second connection (the ad5251 10 k part) is the first tap point where r wb = 231 (r wb = r ab /64 + r w = 156 + 75 ) for data 0x01, and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at r wb = 9893 . see figure 40 for a simplified diagram of the equivalent rdac circuit. the general equation that determines the digitally programmed output resistance between w and b is ad5251: r wb ( d ) = (d /64) r ab + 75 (1) ad5252: r wb ( d ) = (d /256) r ab + 75 (2) where: d is the decimal equivalent of the data contained in the rdac latch. r ab is the nominal end-to-end resistance.
ad5251/ad5252 data sh eet rev. d | page 24 of 28 r ab (%) d (code in decimal) 03823-0-042 0 25 50 75 100 0 16 32 48 63 r wa r wb figure 42 . ad5251 r wa (d) an d r wb (d) vs. decimal code since the digital potentiometer is not ideal, a 75 ? finite wiper resistance is present that can easily be seen when the device is programmed at zero scale. because of the fine geometric and interconnects employed by the device, care should be taken to limit the current conduction between w and b to no more than 5 ma continuous for a total resistance of 1 k ? or a pulse of 20 ma to avoid degradation or possible dest ruction of the device. the maximum dc current for ad5251 and ad52 52 are shown in figure 21 and figure 22, respectively. similar to the mechanical potentiometer, the resistance of the rdac between wiper w and terminal a also produces a digitally controlled complemen tary resistance, r wa . when these terminals are used, the b terminal can be opened. the r wa starts at a maximum value and decreases as the data loaded into the latch increases in value (see figure 42 ). the general equation for th is operation is ad5251: r wa ( d ) = [(64 C d )/64] r ab + 75 ? (3) ad5252: r wa ( d ) = [(256 C d )/256] r ab + 75 ? (4) the typical distribution of r ab from channel - to - channel matches is about 0.15% within a given device. on the other hand, device - to - device m atching is process - lot dependent with a 20% tolerance. programmable potenti ometer operation if all three terminals are used, the operation is called potenti - ometer mode (see figure 43 ); the most common configuration is the volt age divider operation. 03823-0-043 a b w v i v c figure 43 . potentiometer mode configuration if the wiper resistance is ignored, the transfer function is simply ad5251: b ab w v v d v + = 64 (5) ad5252: b ab w v v d v + = 256 (6) a more accurate calc ulation that inclu des the wiper resistance effect is a w ab w ab n w v r r r r d d v 2 2 ) ( + + = (7) where 2 n is the number of steps. unlike in rheostat mode operation, where the tolerance is high, potentiometer mode operation yields an almost ratiometric function of d/2 n wi th a relatively small error contributed by the r w terms. therefore, the tolerance effect is almost cancelled. similarly, the ratiometric adjustment also reduces the temperature coefficient effect to 50 ppm/c, except at low value codes where r w dominates. potentiometer mode operations include other applications , such as op amp input, feedback - resistor networks, and other voltage - scaling applications. the a, w, and b terminals can, in fact, be input or output terminals, provided that |v a |, |v w |, and |v b | do not exceed v dd to v ss .
data sheet ad5251/ad5252 rev. d | page 25 of 28 applications information lcd panel v com adjustment large lcd panels usually require an adjustable v com voltage centered around 6 v to 8 v with 1 v swing and small steps adjustment. this example represents common dac appli - cations where the window of adjustments is small and centered at any level. high voltage and high resolution dacs can be used, but it is far more cost - effective to use low voltage digital potentiometers with level shifting, such as the ad5251 or ad5252, to achiev e the objective. assume a v com voltage requirement of 6 v 1 v with a 20 mv step adjustment, as shown in figure 44 . the ad5252 can be configured in voltage divider mode with an op amp gain. with 20% tolerance accounted for by the ad5252, this circuit can still be adjusted from 5 v to 7 v with an 8 mv/step in the worst case. v dd u1 u2 v com +5v r2 10k? r4 6k? r3 18.5k? r5 1k? r1 350k ? c1 2.2pf b ad5252 +14.4v +14.4v 20% 1% 6v 1v v+ v? 03823-0-044 figure 44 . apply 5 v digital potentiometer ad5251 in a 6 v 1 v application current - sensing amplifier the dual - channel, synchro nous update, and channel - to - channel resistance matching characteristics make the ad5251/ad5252 suitable for current - sensing applications, such as led brightness control. in the circuit shown in figure 45 , when rdac1 and rdac3 are programmed to the same settings, it can be shown that ( ) ref n o v v v d d v + ? ? = 1 2 2 (8) as a result, the current through a sense resistor connected between v 1 and v 2 can be determined. the circuit can be programmed for use with systems that require different s ensitivities. if the op amp has very low offset and low bias current, the major source of error comes from the digital potentiometer channel - to - channel resistance mismatch, which is typically 0.15%. the circuit accuracy is about 9 bits, which is adequate f or led control and other general - purpose applications. u1 v 1 r sense 0.1k ? rdac1 10k ? rdac3 10k ? b b ad5252 ad8628 u2 v o vref +5v v+ v ? 03823-0-045 v 2 figure 45 . current - sensing amplifier adjustable high powe r led driver figure 46 shows a circuit that can drive three or four high power leds. the adp1610 is an adjustable boo st regulator that provides adequate headroom and current for the leds. because its fb pin voltage is 1.2 v, the digital potentiometer ad5252 and the op amp form an average gain of 12 feedback networks that servo the sensing and feedback voltages. as a resu lt, the voltage across r set is regulated around 0.1 v, depending on the ad5252s setting. an adjustable led current is set r led r v i set = (9) r set should be small enough to conserve power, but large enough to limit the maximum led current. r3 should b e used in parallel with the ad5252 to limit the led current to an achievable range. sd sw fb comp ss rt gnd in pwm c c 390pf c ss 10nf r o 100k ? r set 0.25k ? 10k ? w b a c8 0.1 f ad5252 adp1610 v out ad8591 u3 u1 u2 u1 +5v +5v v+ v ? 03823-0-046 r3 200 ? r2 1.1k ? r1 100 ? c3 10 f c2 10 f d1 d1 d2 d3 l1 10 f figure 46 . high power, adjustable led driver
ad5251/ad5252 data sheet rev. d | page 26 of 28 outline dimensions compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 seating plane figure 47. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters
data sheet ad5251/ad5252 rev. d | page 27 of 28 ordering guide model 1 , 2 step r ab (k?) temperature range package description package option ordering quantity AD5251BRU1 64 1 ?40 c to + 105 c 14- lead tssop ru -14 96 AD5251BRU1 - rl7 64 1 ?40 c to +10 5 c 14- lead tssop ru -14 1,000 ad5251bruz1 64 1 ?40 c to + 105 c 14- lead tssop ru -14 96 AD5251BRU10 64 10 ?40 c to + 105 c 14- lead tssop ru -14 96 AD5251BRU10 - rl7 64 10 ?40 c to +10 5 c 14- lead tssop ru -14 1,000 ad5251bruz10 64 10 ?40 c to + 105 c 14- lead tssop ru -14 96 ad5251bru50 - rl7 64 50 ?40 c to + 105 c 14- lead tssop ru -14 1,000 ad5251bruz50 64 50 ?40 c to +10 5 c 14- lead tssop ru -14 96 AD5251BRU100 - rl7 64 100 ?40 c to + 105 c 14- lead tssop ru -14 1,000 ad5251bruz100 64 100 ?40 c to +10 5 c 14- lead tssop ru -14 96 ad5251bruz100 - rl7 64 100 ?40 c to + 10 5 c 14 - lead tssop ru - 14 1,000 ad5252bru1 256 1 ?40 c to +10 5 c 14- lead tssop ru -14 96 ad5252bru1 - rl7 256 1 ?40 c to + 105 c 14- lead tssop ru -14 1,000 ad5252bruz1 256 1 ?40 c to +10 5 c 14- lead tssop ru -14 96 ad 5252bruz1- rl7 256 1 ?40 c to + 105 c 14- lead tssop ru -14 1,000 ad5252bru10 256 10 ?40 c to +10 5 c 14- lead tssop ru -14 96 ad5252bru10 - rl7 256 10 ?40 c to + 105 c 14- lead tssop ru -14 1,000 ad5252bruz10 256 10 ?40 c to +10 5 c 14- lead tssop ru -14 96 ad5252br uz10 - rl7 256 10 ?40 c to + 105 c 14- lead tssop ru -14 1,000 ad5252bru50 256 50 ?40 c to +10 5 c 14- lead tssop ru -14 96 ad5252bru50 - rl7 256 50 ?40 c to + 105 c 14- lead tssop ru -14 1,000 ad5252bruz50 256 50 ?40 c to +10 5 c 14- lead tssop ru -14 96 ad5252bruz50 - rl7 256 50 ?40 c to + 105 c 14- lead tssop ru -14 1,000 ad5252bru100 256 100 ?40 c to +10 5 c 14- lead tssop ru -14 96 ad5252bru100 - rl7 256 100 ?40 c to + 10 5 c 14 - lead tssop ru - 14 1,000 ad5252bruz100 256 100 ?40 c to +10 5 c 14- lead tssop ru -14 96 ad5252bruz 100 - rl7 256 100 ?40 c to + 105 c 14- lead tssop ru -14 1,000 eval - ad5252 sdz 256 10 evaluation board 1 1 in the package marking, line 1 shows the part number . line 2 shows the branding information, such that b1 = 1 k?, b10 = 10 k? , and so on. there is also a # marking for the pb - free part. line 3 shows the date code in yyww . 2 z = rohs compliant part.
ad5251/ad5252 data sh eet rev. d | page 28 of 28 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies con veys a license for the purchaser under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2004 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d03823 - 0 - 9/12(d)

▲Up To Search▲

Price & Availability of AD5251BRU1

	To Download AD5251BRU1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .